1. Technical Field
The present invention relates generally to the field of semi-conductor manufacturing and, more specifically, to a method for forming transistors with raised source and drains.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in CMOS technologies, such as the in the design and fabrication of field effect transistors (FETs). FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.)
One problem with traditional CMOS FET designs is the propensity for these devices to "latch-up." Latch-up is a well known problem caused by unwanted transistor action between elements of the integrated circuit. This unwanted transistor action can be triggered by a wide variety of events, and can cause the semiconductor device to fail.
Latch-up is generally caused by the close proximity of n-channel and p-channel devices in modem CMOS devices. For example, a typical CMOS device fabricated on a p-type substrate would contain a p-channel device fabricated in a n-well (or n-type region) and an n-channel device fabricated in a p-well (or p-type region), with only a short distance between the wells. This structure inherently forms a parasitic lateral bipolar structure (npn) and parasitic vertical bipolar structure (pnp). Under certain biasing conditions the pnp structure can supply base current to the npn structure (or vice versa), causing a large current to flow from one well to the other well. This large current can damage the CMOS device.
The propensity for CMOS devices to latch-up has been addressed in several ways. One way involves reducing the "gain" or beta of the transistor (npn and pnp). This generally reduces the propensity of the CMOS device to latch-up by increasing the trigger voltage/current, where the trigger voltage/current is the voltage/current that must be applied to a node to induce latch-up.
Shallow trench isolation (STI) has been used between the n-channel and p-channel devices to minimize the likelihood of latch-up. However, as device density continues to increase the STI depth tends to decrease. This causes the latch-up holding voltage to be reduced. If the latch-up holding voltage and trigger voltage/current is reduced significantly, i.e., to less than the burn-in voltage, the reliability of the device can be negatively impacted.
One of the bedrock technologies that has allowed FETs to be widely used is the use of gate sidewall spacers. Typical sidewall spacers are formed using a conformal deposition of a spacer material over the gate structure, followed by a directional etch, as disclosed in Pogge, U.S. Pat. No. 4,256,514, "Method for Forming a Narrow Dimensioned Region on a Body," assigned to International Business Machines, Inc. The directional etch removes all the spacer material from the horizontal surfaces, but leaves "spacers" at the sidewalls of the gates. These spacers are inherently self-aligned with the gate.
Unfortunately, the sidewall spacer has a limited ability to be scaled to smaller dimensions. For example, in traditional methods of creating a sidewall spacers is that the process for forming spacers results in spacers on all exposed sidewalls of a structure. If a spacer is not desired on a particular sidewall, it must be removed with additional processing steps. These additional processing steps are not self aligned, and thus result in additional unwanted process variations.
Thus, there is a need for improved methods of increasing latch-up immunity of CMOS devices, and a need for methods to form source/drain regions with lower leakage and junction capacitance, and integratable with standard processes and structures. There is an additional need for improved methods of forming sidewall spacers that are used in these CMOS devices.